Senior Engineer


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Job Description

About Silicon Labs:

We are a leader in secure, intelligent wireless technology for a more connected world. Our integrated hardware and software platform, intuitive development tools, unmatched ecosystem and robust support make us the ideal long-term partner in building advanced industrial, commercial, home and life applications. We make it easy for developers to solve complex wireless challenges throughout the product lifecycle and get to market quickly with innovative solutions that transform industries, grow economies and improve lives.

What we’re looking for:

IoT Digital IC Design Team at Silicon Labs

The IoT Digital team is a state-of-art IC design team focused on producing world-class Wireless MCU SoCs. The architecture specification, design, verification, and implementation of the Wireless MCU SoCs is the responsibility of the IoT Digital team. These SoCs include an embedded CPU system with analog and digital peripherals, advanced security, state-of-the-art power management, and best-in-class radios to support a wide range of wireless IoT applications and standards.

As Verification Engineer, you will be working closely with the IC Design, System, and Architecture teams to develop and execute the verification plan for the next generation of IoT chips.

Skills you’ll need:

  • Block and IP Verification
  • Block-level verification to validate block performance and adherence to requirements
  • Generate and execute verification plan based on specifications
  • Architect and implement test benches using UVM-based constrained-random and formal methods
  • Coverage definition, implementation, and analysis
  • Formal Verification of mixed-signal IP integration, including real-number modeling
  • SoC Integration and Verification
  • Define, test and debug use cases for the SoC
  • Verify and debug low-power design
  • Flows and Methodology
  • Improve flows and methodologies to streamline IP development and integration.

Qualification & Requirements

  • Min. 5 years of IC design experience for senior positions. Open to junior candidates with strong foundation.
  • Industry experience developing test benches and verification components with SystemVerilog and UVM is required
  • Knowledge of scripting/language (Python, PERL, shell, TCL)
  • Design/Verification skills such as Software/Firmware coding (C), SystemVerilog Assertion and coverage analysis, Low-power implementation (UPF), Mixed Signal Real Number Modeling (RNM, Spice)

Benefits & Perks:

Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun.

  • Employee Stock Purchase Plan (ESPP)
  • Insurance plans with Outpatient cover
  • Flexible work policy
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