JL Semi is pushing the boundary of automotive and industry Ethernet technology. Innovations in silicon architecture & design coupled with advance process nodes, our products deliver industry leading performance in range, resilience and power consumption.
Located in the heart of Asia's high-tech hubs - Shanghai, Shenzhen and Singapore - we are looking for talents to join our journey for rapid growth.
For this role, we are seeking qualified PLL designers to work on the next generation PLLs for our leading PHY/SERDES products. Our analog/mixed-signal team involved in design and productization on leading-edge CMOS process technology nodes are expanding.
What will you be working on:
1. Design of building blocks for PLL, DLL etc
2. Work closely with mask design team to implement layout view of designs
3. Complete top-level spice and mixed-mode simulations to validate top-level integration
4. Review ATE and lab test results to resolve yield issues and drive bug fixes
5. Work with system teams in system bringup and debug
What are we looking for:
1. Experience in design of mixed-signal circuit building blocks for PLL, DLL, and clock distribution for high-speed interfaces.
2. Experience in VCO design including ring VCOs and LC VCOs
3. Good knowledge of bandgaps, bias, op-amps, LDOs, feedback and compensation techniques as well as digitally assisted analog circuit techniques
4. Provide schematic layout guidance to mask designer and perform post-layout simulation.
5. Pre-layout and post-layout design optimization to meet specifications across PVT, sensitivity, aging, electromigration simulation tests.
6. Lab and ATE test plans and measurement for characterization, and volume production
7. Strong and effective communication skills and team spirit
8. MSEE 3+ yrs in related area of expertise or PhD